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INTEGRATED CIRCUITS
DATA SHEET
UDA1343TT Economy audio CODEC with features
Preliminary specification File under Integrated Circuits, IC01 2000 Jan 12
Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
FEATURES General * Low power consumption * 2.4 V to 3.6 V power supply range, with 3 V typical * 5 V tolerant TTL compatible digital inputs * 256, 384 and 512fs system clock * Supports sampling frequencies from 8 to 110 kHz * Non-inverting ADC plus integrated high-pass filter to cancel DC offset * The ADC supports 2 V (RMS) input signals * Stereo PGA with 0 to 24 dB gain in 3 dB steps * Overload detector for easy record level control * Separate power control for ADC + PGA and DAC * Integrated digital interpolation filter plus non-inverting DAC * Functions controllable by L3 microcontroller interface * Small package size (TSSOP28) * ADC and DAC output polarity can be set. Multiple format input interface * I2S-bus, MSB-justified up to 24 bits and LSB-justified 16, 18, 20 and 24 bits format compatible * Four combined data formats with MSB data output and LSB 16, 18, 20 and 24 bits data input * 1fs input and output format data rate. DAC digital sound processing * Digital dB-linear volume control (low microcontroller load) via L3 microcontroller in 0.25 dB steps * Digital de-emphasis for 32, 44.1, 48 and 96 kHz * Cosine roll-soft mute. Advanced audio configuration * Stereo single-ended input configuration * Stereo line output (under microcontroller volume control), no post filter required ORDERING INFORMATION TYPE NUMBER UDA1343TT PACKAGE NAME TSSOP28 DESCRIPTION GENERAL DESCRIPTION
UDA1343TT
* High linearity, dynamic range and low distortion * Digital silence detector * Digital mixer for mixing ADC signal and playback signal * ADC volume control in 0.25 dB steps and cosine roll-off mute. APPLICATIONS * Portable equipment which includes audio functions * Digital video camera.
The UDA1343TT is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with basic signal processing features employing bitstream conversion techniques. The low power consumption, the small package size and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. The UDA1343TT is equipped with a digital mixer for mixing the ADC signal directly to the playback signal (for example for Karaoke applications). In the mixing mode the ADC output signal can be output before or after the mixer. The mixer can also be used as a selector to select between the ADC or the digital data being played back at the DAC.
VERSION SOT361-1
plastic shrink small outline package; 28 leads; body width 4.4 mm
2000 Jan 12
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
QUICK REFERENCE DATA SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) IDDA(DAC) IDDO(DAC) IDDD ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current DAC operational amplifier supply current digital supply current 2.4 2.4 2.4 - - - - - - - - -40 - - - - - - - - - - - - - - - - PARAMETER CONDITIONS MIN.
UDA1343TT
TYP. 3.0 3.0 3.0 10 100 4 50 2.5 200 5 300 - 1.0 -85 -81 -37 -35 97 95 100 900 -85 -80 -37 -35 100 100 98
MAX. 3.6 3.6 3.6 - - - - - - - - +85 - - - - - - - - - - - - - - - -
UNIT V V V mA A mA A mA A mA A C V dB dB dB dB dB dB dB mV dB dB dB dB dB dB dB
operating mode ADC power-down operating mode DAC power-down operating mode DAC power-down operating mode ADC plus DAC power-down
Tamb Vi(rms) (THD + N)/S
ambient temperature input voltage (RMS value) notes 1, 2 and 3 total harmonic distortion-plus-noise to at 0 dB signal ratio fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz signal-to-noise ratio Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz channel separation output voltage (RMS value) total harmonic distortion-plus-noise to at 0 dB signal ratio fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz channel separation signal-to-noise ratio code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz
Analog-to-digital converter
S/N
cs Vo(rms) (THD + N)/S
Digital-to-analog converter
cs S/N
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
SYMBOL Power performance PADDA PDA PAD PPD Notes
PARAMETER power consumption in record and playback mode power consumption in playback mode power consumption in record mode power consumption in power-down mode
CONDITIONS
MIN. - - - -
TYP. 64 36 46 2.0
MAX. - - - -
UNIT mW mW mW mW
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply. 3. The performance figures and input voltage of the ADC are given with the PGA gain set to 0 dB.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
BLOCK DIAGRAM
UDA1343TT
handbook, full pagewidth
VDDA(ADC) VSSA(ADC) 2 3 1
VADCP 7
VADCN 6
Vref(A) 4 PGA 5 VINR
VINL
PGA
ADC
ADC 8 TEST1 TEST2 RESET
VDDD VSSD
10 11
DECIMATION FILTER
21 20
DC/VOLUME/MUTE 18 16 17 19 DIGITAL INTERFACE L3-BUS INTERFACE 13 14 15 12
DATAO BCK WS DATAI
L3MODE L3CLOCK L3DATA SYSCLK
OVERFL
9
DE-EMPHASIS/VOLUME/MUTE DIGITAL MIXER DIGITAL SILENCE DETECTOR
INTERPOLATION FILTER
UDA1343TT
NOISE SHAPER
DAC
DAC
VOUTL
26
24
VOUTR
25 VDDO
27 VSSO
23 VDDA(DAC)
22 VSSA(DAC)
28 Vref(D)
MGL886
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
PINNING SYMBOL VSSA(ADC) VDDA(ADC) VINL Vref(A) VINR VADCN VADCP TEST1 OVERFL VDDD VSSD SYSCLK L3MODE L3CLOCK L3DATA BCK WS DATAO DATAI RESET TEST2 VSSA(DAC) VDDA(DAC) VOUTR VDDO VOUTL VSSO Vref(D) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 analog ground pad analog supply pad analog input pad analog pad analog input pad analog pad analog pad 5 V tolerant digital input pad with internal pull-down pad 5 V tolerant slew-rate controlled digital output pad digital supply pad digital ground pad 5 V tolerant digital Schmitt triggered input pad digital input pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital Schmitt triggered input with pull down, slew rate controlled output pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant slew-rate controlled digital output pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital Schmitt triggered input pad with internal pull down 5 V tolerant digital input pad with internal pull-down pad analog ground pad analog supply pad analog output pad analog supply pad analog output pad analog ground pad analog pad TYPE
UDA1343TT
DESCRIPTION ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage test pin 1 ADC overload output digital supply voltage digital ground system clock input 256, 384 or 512fs L3MODE input L3CLOCK input L3DATA input bit clock input word select input data output data input reset input test pin 2 DAC analog ground DAC analog supply voltage DAC output right operational amplifier supply voltage DAC output left operational amplifier ground DAC reference voltage
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Reset
handbook, halfpage
UDA1343TT
VSSA(ADC) 1
28 Vref(D) 27 VSSO 26 VOUTL 25 VDDO 24 VOUTR 23 VDDA(DAC)
VDDA(ADC) 2 VINL 3 Vref(A) 4 VINR 5 VADCN 6 VADCP 7
Pin 20 is a reset pin (active HIGH), which resets the internal digital core of the IC and also resets all feature values of the L3 interface to their default settings as given in Tables 8 and 9. Since the RESET pin is a pull-down pad with Schmitt-trigger, a Power-On Reset (POR) function can be made by connecting this pin to the digital power supply via a capacitor. Note: care must be taken that during the HIGH period of the reset signal it is best to have at least 8 SYSCLK clock cycles to properly reset the device. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1343TT consists of two 5th-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 64. Analog front-end The analog front-end is equipped with a Programmable Gain Amplifier (PGA) which can be controlled via the L3 interface. The control range is from 0 dB to 24 dB gain in 3 dB steps independant for left and right. In applications in which a 2 V (RMS) input signal is used, a 12 k resistor must be connected in series with the input of the ADC. This makes a voltage divider with the internal ADC resistor and makes sure only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch of the PGA must be set to 6 dB via the L3 interface. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1. Table 1 Application modes using input gain stage PGA GAIN 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS)
UDA1343TT
TEST1 8 OVERFL 9 VDDD 10 VSSD 11 SYSCLK 12 L3MODE 13 L3CLOCK 14
MGL887
22 VSSA(DAC) 21 TEST2 20 RESET 19 DATAI 18 DATAO 17 WS 16 BCK 15 L3DATA
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The UDA1343TT accommodates slave mode only, this means that in all applications the system devices must provide the system clock and the serial audio clock signals. The system clock must be locked in frequency to the digital interface input signals. The BCK clock can be up to 128fs, or in other words the BCK frequency fBCK is 128 times the Word Select (WS) frequency fWS or less: fBCK = < 128 x fWS. Important: the WS edge MUST fall on the negative edge of the BCK at all times for correct operation of the digital I/O data interface. Note: the sampling frequency range is from 8 to 110 kHz, however for the 512fs clock mode the sampling range is from 8 to 55 kHz.
RESISTOR (12 k) Present Present Absent Absent
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Decimation filter (ADC) The decimation from 64fs to 1fs is performed in two stages. sin x The first stage realizes a 4th-order ----------- characteristic. x This filter decreases the sample rate by 16. The second stage consists of 2 half-band filters and a recursive filter, each decimating by a factor of 2. Table 2 Digital decimation filter characteristics ITEM Pass-band ripple Stop band Dynamic range Overall gain with 0 dB input to the ADC CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.05 -50 114 -1.16
1
UDA1343TT
Digital silence detector The UDA1343 is equipped with a digital silence detector on the digital data input. This detects whether a certain amount of consecutive samples are 0. The status of the digital silence detector can be read from the microcontroller interface. The number of samples can be set via the L3 interface to 3200, 4800, 9600 or 19600 samples. Mute Muting the DAC will result in a cosine roll-off soft mute, using 32 x 4 = 128 samples (at 44.1 kHz this is 3 ms). The cosine roll-off curve is illustrated in Fig.3.
MGS755
In the ADC path there is a volume control with a range of 0 dB to -66 dB and - dB in 0.25 dB steps, and a cosine roll-off soft mute. Note: it should be noted that the digital output level is inversely proportional to the ADC analog power supply. This means that with a constant analog input level and increasing analog power supply, the digital output level will decrease proportionally. Overload detection (ADC) In practice the output is used to indicate whenever the output data, in either the left or right channel, is larger than -1 dB (the actual figure is -1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output (pin 9) is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. Interpolation filter (DAC) The digital filter interpolates from 1 to 128fs by means of a cascade of a recursive filter and an FIR filter. Table 3 Digital interpolation filter characteristics ITEM Pass-band ripple Stop band Dynamic range Gain CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.03 -65 116.5 -3.5
handbook, halfpage
mute factor 0.8
0.6
0.4
0.2
0 0 1 2 t (ms) 3
Fig.3 Mute as a function of raised cosine roll-off.
Double speed SInce the device supports a sampling range of 8 to 110 kHz, the device can support double speed (e.g. for 44.1 kHz and 48 kHz) by just doubling the system speed. In double speed all features are available.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Digital mixer The UDA1343TT has a digital mixer which can mix the ADC signal to the playback signal. A functional block diagram of the mixer mode is given in Fig.4. When the device is in mixer mode, care is taken to avoid clipping. This is done by reducing both signals by -6 dB before mixing. After mixing there is master volume and mute, after which the signal is reamplified digitally by 6 dB. The codec can be set to mixer mode via the L3 interface by setting the MIX bit HIGH.
UDA1343TT
In the mixer mode there are 3 volume and mute controls available; one for the ADC channel, one for the playback channel and one for the master (equal sum) signal. All three volume ranges can be controlled in 0.25 dB steps. In the mixer mode, the ADC volume control is used for mixing purposes. The decimator output signal can be output from the chip before the ADC volume control or after the ADC volume control. This can be set via the L3 interface using the ADC output select bit.
handbook, full pagewidth
ADC volume + mute DIGITAL DC FILTER VOLUME + MUTE -6 dB
master volume + mute
from ADC and decimator
+
-6 dB
VOLUME + MUTE
+6 dB
to interpolator and DAC
UDA1343TT
ADC_OUT select (L3) VOLUME + MUTE I2S-bus volume + mute
MGL888
I2S-bus output
I2S-bus input
Fig.4 Mixing feature in the UDA1343TT.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Digital output signal The output to the digital output of the UDA1343TT can be selected from 3 positions, using the two bits ADC_OUT select in the L3 microcontroller interface. The 3 positions are as follows: * Directly from the ADC and decimator (default) * After volume control and mute in the ADC data path * After the digital mixer and before master volume control and mute. It should be noted that this output is before the +6 dB gain. This is done in order to prevent clipping at the mixer output at all times. Noise shaper (DAC) The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). The Filter Stream DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier.
UDA1343TT
In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. Multiple format input/output audio interface The digital audio interface supports multiple standards: * I2S-bus with data word length of up to 24 bits * MSB-justified serial format with data word length of up to 24 bits * LSB-justified data formats with word lengths of 16, 18, 20 and 24 bits. * Four combined data formats with MSB data output and 16, 18, 20 and 24 LSB data input. The digital audio interface formats are illustrated in Fig.5.
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dbook, full pagewidth
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Philips Semiconductors
Economy audio CODEC with features
WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT
>=8
DATA
MSB
B2
MSB
B2
MSB
INPUT FORMAT I2S WS 1 BCK 2 LEFT 3 >=8 1 2 RIGHT 3 >=8
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT WS LEFT 16 BCK 15 2 1 RIGHT 16 15 2 1
DATA
MSB
B2
B15 LSB LSB JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 18 17 16 15 2 1
RIGHT 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B17 LSB LSB JUSTIFIED FORMAT 18 BITS
MSB
B2
B3
B4
B17 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
Preliminary specification
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT
UDA1343TT
20
19
18
17
16
15
2
1
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MBK983
Fig.5 The digital audio interface formats.
Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
L3 INTERFACE Introduction The UDA1343TT has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: * System clock frequency * Data input format * Power control * DC filtering * De-emphasis * Volume: master volume, I2S-bus mixer volume and ADC volume * Mute: master mute, I2S-bus mute and ADC mute * Mixer settings * PGA gain settings * Digital silence control settings * Polarity settings of the ADC and the DAC. The exchange of data and control information between the microcontroller and the UDA1343TT is accomplished through a serial hardware interface comprising the following pins: * L3DATA: microcontroller interface data line * L3MODE: microcontroller interface mode line * L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is organized LSB first, and in accordance with the so called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Fig 6). Important: when the device is powered-up, at least one L3CLOCK pulse must be sent to the L3 interface to wake-up the interface prior to sending to the device. This is only needed once after the device is powered-up. Device addressing The device addressing mode is used to select a device for subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits. The fundamental timing is illustrated in Fig.6.
UDA1343TT
Basically, 2 types of transfer can be defined; data transfer to the device and data transfer from the device; see Table 4. Table 4 DOM BIT 1 0 0 1 1 Selection of data transfer DOM BIT 0 0 1 0 1 not used not used DATA and STATUS write or pre-read DATA and STATUS read TRANSFER
As can be seen in Table 4, the DATA and STATUS read and write actions are combined. The device address consists of one byte, which is split up into two parts: * Bits 7 to 2 represent a 6-bit device address * Bits 1 and 0 represent the type of data transfer according to Table 4. As can be seen in Table 4, there are two types of data transfers, being DATA and STATUS which can be read and written. Register addressing After sending the device address, including the flags (the DOM bits) whether the information is read or written, one byte is sent with the destination register address using 7 bits, and 1 bit which signals whether information will be read or written. The fundamental timing for the data mode is illustrated in Fig.7. Basically there are 3 cases for register addressing: 1. Register addressing for L3 write: the first bit is at logic 0 indicating a write action to the destination register, and is followed by 7 register address bits. 2. Prepare read addressing: the first bit of the byte is at logic 1, signalling data will be read from the register indicated. 3. The read action itself: in this case the device returns a register address prior to sending data from that register. When the first bit of the byte is at logic 0, the register address is valid, if the first bit is at logic 1 the register address is invalid.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Data write mode For writing data to a device four bytes must be sent. The data write mode is illustrated in Fig.8. 1. One byte with the device address including `01' for signalling write to the device. 2. One byte starting with a logic 0 for signalling write followed by 7 bits indicating the destination address. 3. Two data bytes. Notes: 1. Each time a new destination address needs to be written, the device address must sent again. 2. When addressing the device for the first time after power-up of the device, at least one L3 clock cycle must be sent to enable the L3 interface. Data read mode For reading from the device, a prepare-read must first be done. After the prepare-read, the device address is sent again. The device then returns with the register address, indicating whether the address was valid or not, and the data of the register. This procedure is explained below, and an example transmission is illustrated in Fig.9.
UDA1343TT
1. One byte with the device address including `01' for signalling write to the address. 2. One byte is sent with the register address which needs to be read. This byte starts with a logic 1, which indicated that there will be a read action from the register. 3. One byte with the device address including `11' is sent to the device. The `11' indicates that the device must write data to the microcontroller. 4. The device now writes the requested register address to the bus, indicating whether the requested register was valid or not (logic 0 means valid, logic 1 means invalid). 5. The device writes the data from the requested register to the bus (two bytes).
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.6 Timing address mode.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA L3DATA write
tsu(L3)DA
th(L3)DA
BIT 0
BIT 7
L3DATA read ten(L3)DA tsu(L3)R th(L3)R tdis(L3)DA
MGL889
Fig.7 Data write and read mode timing.
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L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 0/1 register address data byte 2 data byte 2 valid/non-valid send by the device
MGL890
Philips Semiconductors
Economy audio CODEC with features
L3 wake-up pulse after power-up
L3CLOCK
L3MODE device address L3DATA 0 1 0
MGS753
register address
data byte 1
data byte 2
DOM bits
write
Fig.8 Data write mode for L3 version 2.
Preliminary specification
UDA1343TT
Fig.9 Data read mode for L3 version 2.
Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
L3 protocol WARNING Write followed by read
UDA1343TT
When issuing a read command following a write command, at least 8 s delay must be inserted to allow the write to take effect. No further restrictions apply to the order of L3 read and write commands. Table 5 L3 data WRITE FIRST IN TIME MODE DATA BIT 0 Addressing mode device address Data transfer 1 Data transfer 2 Data transfer 3 Table 6 register address MS data byte LS data byte 0 0 (write) D15 D7 BIT 1 1 A6 D14 D6 BIT 2 1 A5 D13 D5 BIT 3 1 A4 D12 D4 BIT 4 1 A3 D11 D3 BIT 5 0 A2 D10 D2 BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0 LATEST IN TIME
L3 prepare READ DATA FIRST IN TIME LATEST IN TIME BIT 3 1 A4 BIT 4 1 A3 BIT 5 0 A2 BIT 6 0 A1 BIT 7 0 A0 DATA BIT 0 BIT 1 1 A6 BIT 2 1 A5 0 1 (read)
MODE
Addressing mode device address Data transfer 1 Table 7 register address
L3 READ DATA FIRST IN TIME LATEST IN TIME BIT 3 1 A4 D12 D4 BIT 4 1 A3 D11 D3 BIT 5 0 A2 D10 D2 BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0 DATA BIT 0 BIT 1 1 A6 S14 D6 BIT 2 1 A5 D13 D5 1 0 = valid 1 = invalid D15 D7
MODE
Addressing mode device address Data transfer 1 Data transfer 2 Data transfer 3 register address MS data byte LS data byte
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Economy audio CODEC with features
L3 REGISTER MAPPING Table 8 REG NUM L3 register mapping including default register settings; bits D15 to D8 FUNCTION D15 D14 D13 D12 D11 D10 D9 D8
Writable and readable registers 00H system setting 0 11H 12H MASTER volume control silence detector ADC output select 13H ADC volume I2S-bus volume mute de-emphasis ADC settings 0 PON-R ADC 1 software reset 0 PON-L ADC 1 0 PON BIAS 1 0 0 0 0 0 MTM 0 MT-ADC 0 DCfilt1 0 MT-IIS 0 DCfilt0 0 mixer 0 VC-AD7 0 0 VC-AD6 0 0 VC-AD5 0 0 VC-AD4 0 0 VC-ADC3 0 0 VC-ADC2 0 0 0 0 POLinv DAC POLinv ADC 0 0 0 0 PON DAC 1 0 0 0 SC1 1 0 ADC_out Select1 0 VC-ADC1 0 SC0 1 0 ADC_out Select0 0 VC-ADC0 0
writing this sets all controllable settings to their default values
Readable registers Preliminary specification interpolator
UDA1343TT
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Economy audio CODEC with features
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Writable and readable registers 00H system setting 0 11H 12H 13H 14H MASTER volume control silence detector ADC output select ADC volume I2S-bus mixer volume mute de-emphasis 20H ADC settings 0 PGAL3 0 7FH software reset 0 PGAL2 0 0 PGAL1 0 0 PGAL0 0 0 PGAR3 0 0 VC-IIS7 0 0 VC-IIS16 0 0 VC-IIS5 0 0 VC-IIS4 0 0 VC-IIS3 0 VC7 0 1 VC6 0 SFOR3 0 VC5 0 SFOR2 0 VC4 0 SFOR1 0 VC3 0 SFOR0 0 VC2 0 SDET1 0 VC-IIS2 0 DE2 0 PGAR2 0 VC1 0 SDET0 0 VC-IIS1 0 DE1 0 PGAR1 0 MIX 0 VC0 0 SDET_on 1 VC-IIS0 0 DE0 0 PGAR0 0
Readable registers 18H interpolator SDET-IIS-R SDET-IIS-L MTM state MT-ADC state MT-IIS state
Preliminary specification
UDA1343TT
Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
POLARITY CONTROL OF THE DAC A 1-bit value to program the DAC output polarity. Table 10 Polarity control of the DAC POLINV DAC 0 1 POLARITY CONTROL OF THE ADC A 1-bit value to program the ADC output polarity. Table 11 Polarity control of the ADC POLINV ADC 0 1 POWER CONTROL OF THE DAC A 1-bit value to program the power setting of the DAC. FUNCTION ADC output is not inverting ADC output is inverting FUNCTION DAC output is not inverting DAC output is inverting SYSTEM CLOCK SETTINGS Table 12 Power control of the DAC PON DAC 0 1
UDA1343TT
FUNCTION DAC powered down DAC powered up
A 2-bit value (SC1 and SC0) to select the required external clock frequency (see Table 13). Table 13 System clock frequency settings SC1 0 0 1 1 DATA INPUT FORMAT A 3-bit value (SFOR3 to SFOR0) to select the required data format (see Table 14). SC0 0 1 0 1 FUNCTION 512fs 384fs 256fs
Table 14 : Data input format settings SFOR3 0 0 0 0 0 0 0 0 1 1 1 MIXER SETTING A 1-bit value to enable or disable the digital mixer (for mixing the ADC signal to the playback signal). Table 15 Mixer setting MIX 0 1 FUNCTION mixer disabled mixer enabled SFOR2 0 0 0 0 1 1 1 1 0 0 : SFOR1 0 0 1 1 0 0 1 1 0 0 : SFOR0 0 1 0 1 0 1 0 1 0 1 : I2S-bus LSB-justified; 16 bits LSB-justified; 18 bits LSB-justified; 20 bits MSB-justified MSB-justified output/LSB-justified 16 bits input MSB-justified output/LSB-justified 18 bits input MSB-justified output/LSB-justified 20 bits input MSB justified output/ LSB-justified 24 bits input LSB justified, 24 bits other codes are reserved for future use FUNCTION
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
ADC OUTPUT SELECTOR
UDA1343TT
A 1-bit value to set the ADC I2S-bus output signal, being either before or after the mixer volume control and mute. Table 16 ADC output select ADC_OUT_SELECT1 0 0 1 1 MASTER VOLUME CONTROL An 8-bit value to program the left and right channel master volume attenuation (VC5 to VC0). The range is 0 dB to - dB in steps of 0.25 dB (see Table 17). Table 17 Master volume control: volume settings interpolator core VC7 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VC6 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VC5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VC4 0 0 0 0 0 0 0 1 1 1 1 0 0 1 VC3 0 0 0 0 0 1 1 0 0 1 1 0 0 1 VC2 0 1 1 1 1 0 1 0 1 0 1 0 1 1 VC1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 VC0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 VOLUME (dB) 0 0 -0.25 -0.5 -0.75 -1 : -50 -52 -54 -57 -60 -66 - - SILENCE DETECTOR ENABLE SETTING A 1-bit value to enable or disable the digital silence detection signal. Table 19 Silence detector control setting FUNCTION 3200 samples 4800 samples 9600 samples 19600 samples SDET_ON 0 1 FUNCTION silence detector disabled silence detector enabled ADC_OUT_SELECT0 0 1 0 1 FUNCTION digital output before the ADC volume and mute digital output after ADC volume control and mute digital output after the mixer not used
SILENCE DETECTOR SAMPLES SETTING A 2-bit value to set the number of samples for the digital silence detector circuit. Table 18 Silence detector settings SDET1 0 0 1 1 SDET0 0 1 0 1
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
ADC AND IIS MIXER VOLUME CONTROL
UDA1343TT
An 8-bit value to program the volume ADC attenuation. The range is 0 dB to - dB in steps of 0.25 dB (see Table 20). Table 20 Mixer volume settings. VC-AD7 VC-IIS7 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VC-AD6 VC-IIS6 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VC-AD5 VC-IIS5 0 0 0 0 0 0 1 1 1 0 0 0 0 1 VC-AD4 VC-IIS4 0 0 0 0 0 0 1 1 1 0 0 0 0 1 VC-AD3 VC-IIS3 0 0 0 0 0 0 0 1 1 0 0 1 1 1 VC-AD2 VC-IIS2 0 1 1 1 1 1 1 0 1 0 1 0 1 1 Table 22 Mixer mute MT-ADC/MT-IIS 0 1 DIGITAL DE-EMPHASIS MTM 0 1 MIXER MUTE CONTROL Two 1-bit values to enable the digital mutes of the mixer. These signals can be used to independently mute the I2S-bus playback signal or the signal coming from the ADC. These mute functions can only be used in the mixer mode when the MIX bit is set HIGH. The MT-ADC and MT-IIS bits can also be used to select either the I2S-bus or the ADC signal for playback. FUNCTION no muting muting A 2-bit value to enable the digital de-emphasis filter. Table 23 De-emphasis settings DE2 0 0 0 0 1 1 1 1 DC FILTER 2000 Jan 12 21 DE1 0 0 1 1 0 0 1 1 DE0 0 1 0 1 0 1 0 1 FUNCTION no de-emphasis de-emphasis; 32 kHz de-emphasis; 44.1 kHz de-emphasis; 48 kHz de-emphasis; 96 kHz not used FUNCTION no muting muting VC-AD1 VC-IIS1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 VC-AD0 VC-IIS0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 VOLUME (dB) 0 0 -0.25 -0.5 -0.75 -1 : -44 -46 -48 -51 -54 -60 - -
MASTER MUTE CONTROL A 1-bit value to enable the digital master mute. This mute control signal mutes the master playback signal after mixing. Table 21 Master mute
A 1-bit value to enable the digital DC filter (see Table 24).
Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Table 24 DC filtering; note 1 DC1 0 0 1 1 Note 1. The corner frequencies of the DC filter are given assuming 44.1 kHz sampling frequency. ADC POWER CONTROL Three 1-bit value to disable the ADC to reduce power consumption. Table 25 Power control settings PON BIAS 0 1 1 1 PGA GAIN SETTINGS PON-R ADC x 0 1 1 PON-L ADC x 1 0 1 FUNCTION DC0 0 1 0 1 no DC filtering DC filtering with -3 dB at 3 Hz DC filtering with -3 dB at 100 Hz DC filtering with -3 dB at 200 Hz FUNCTION
UDA1343TT
both ADC channels off and also bias block turned off ADC left channel powered on, bias block turned on ADC right channel powered on, bias block turned on both left and right ADC channels enabled, bias block turned on
Two 4-bit values to program the PGA gain settings. The PGA settings can be set individually for the left and the right channels. Table 26 PGA gain control settings PGAL3, PGAR3 0 0 0 0 0 0 0 0 1 1 PGAL2, PGAR2 0 0 0 0 1 1 1 1 0 : PGAL1, PGAR1 0 0 1 1 0 0 1 1 0 : PGAL0, PGAR0 0 1 0 1 0 1 0 1 0 : FUNCTION 0 dB gain 3 dB gain 6 dB gain 9 dB gain 12 dB gain 15 dB gain 18 dB gain 21 dB gain 24 dB gain not used
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
L3 readable registers
UDA1343TT
The L3 interface also contains some read-only registers in which system status can be read. The read-only registers are given in Table 27. It should be noted that all bits mentioned in the table are active HIGH. Table 27 Description of the bits from the READ ONLY registers NAME SDET-IIS-L SDET-IIS-R MTM_state MT-ADC_state MT-IIS_state signals whether the output data of the signals whether there is master mute signals whether there is mute in the ADC channel signals whether there is mute in the I2S-bus input channel FUNCTION I2S-bus left channel is digitally zero signals whether the output data of the I2S-bus right channel is digitally zero
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltages referenced to ground; VDDD = VDDA = VDDO = 3 V; Tamb = 25 C; unless otherwise specified. SYMBOL VDDD Txtal(max) Tstg Tamb Ves PARAMETER digital supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage note 1 CONDITIONS MIN. - - -65 -40 MAX. 5.0 150 +125 +85 UNIT V C C C
human body model; note 2 machine model; note 2
Note 1. All VDD and VSS connections must be made to the same power supply. 2. According to JEDEC II specification. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 110 UNIT K/W
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
DC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; Tamb = 25 C; RL = 5 k; note 1; all voltages referenced to ground; unless otherwise specified. SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) IDDA(DAC) IDDO(DAC) IDDD ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current DAC operational amplifier supply current digital supply current operating mode ADC power-down operating mode DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down Digital input pins (5 V tolerant TTL compatible) VIH VIL VIH(th) VIL(th) Vhys ILI Ci VIL VOH VOL Vref(A) Ro(refA) Ri Ci Vref(D) Ro(refD) Ro HIGH-level input voltage LOW-level input voltage HIGH-level threshold input voltage LOW-level threshold input voltage Schmitt trigger hysteresis input leakage current input capacitance LOW-level input voltage IOH = -2 mA IOL = 2 mA referenced to VSSA(ADC) fi = 1 kHz 2.0 -0.5 1.3 0.9 0.4 - - -0.5 - - - - - - - - 5.0 0.8 1.9 1.35 0.7 10 10 0.2VDDD - 0.4 V V V V V A pF V 2.4 2.4 2.4 - - - - - - - - 3.0 3.0 3.0 10 100 4 50 2.5 200 5 300 3.6 3.6 3.6 - - - - - - - mA A V V V mA A mA A mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital output pins HIGH-level output voltage LOW-level output voltage 0.85VDDD - - - V V
Analog-to-digital converter reference voltage Vref(A) reference output resistance input resistance input capacitance 0.45VDDA 0.5VDDA - - - referenced to VSSA(DAC) 24 9.8 20 0.55VDDA V - - - k k pF
Digital-to-analog converter reference voltage Vref(D) reference output resistance DAC output resistance 0.45VDDA 0.5VDDA - - 28 0.13 0.55VDDA V - 3.0 k
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
SYMBOL Io(max) RL CL Notes
PARAMETER maximum output current load resistance load capacitance
CONDITIONS (THD + N)/S < 0.1% RL = 800 note 2 - 3 -
MIN.
TYP. 3.5 - - - -
MAX.
UNIT mA k pF
200
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven, a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - - - - - - - - - - MIN. TYP. - - - - - - - - - - MAX. UNIT
Analog-to-digital converter Vi(rms) Vi (THD + N)/S input voltage (RMS value) note 1 unbalance between channels total harmonic at 0 dB distortion-plus-noise to signal ratio fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz signal-to-noise ratio Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz channel separation power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 1% 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting 1.0 0.1 -85 -81 -37 -35 97 95 100 30 V dB dB dB dB dB dB dB dB dB
S/N
cs PSRR
Analog-to-digital converter using PGA Vi(rms) input voltage (RMS value) - - - - - - - - - 1000 708 500 354 250 178 126 89 63 - - - - - - - - - mV mV mV mV mV mV mV mV mV
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
SYMBOL (THD + N)/S
PARAMETER
CONDITIONS - - - - - - - - -
MIN.
TYP. -85 tbf tbf tbf tbf tbf tbf tbf tbf - - - - - - - - -
MAX.
UNIT dB dB dB dB dB dB dB dB dB
total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal ratio 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting fs = 44.1 kHz; at -60 dB; A-weighted 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting Vi = 0 V; A-weighted; at 44.1 kHz
S/N
signal-to-noise ratio
- - - - - - - - - -
-37 tbf tbf tbf tbf tbf tbf tbf tbf 97
- - - - - - - - - -
dB dB dB dB dB dB dB dB dB dB
Digital-to-analog converter Vo(rms) Vo (THD + N)/S output voltage (RMS value) unbalance between channels total harmonic at 0 dB distortion-plus-noise to signal ratio fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz cs S/N channel separation signal-to-noise ratio code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz A-weighted; digital silence PSRR Note 1. The performance figures and input voltage given are with the PGA gain set to 0 dB. power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 1% - - - - - - - - - - - 900 0.1 -85 -80 -37 -35 100 100 98 110 60 - - - - - - - - - - - mV dB dB dB dB dB dB dB dB dB dB
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
UDA1343TT
AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing; see Fig.10 Tsys system clock cycle fsys = 256fs, note 1 fsys = 384fs, note 1 fsys = 512fs, note 2 tCWL tCWH tr tf tBCK tBCKH tBCKL tr tf ts(DATAI) th(DATAI) fsys LOW level pulse width fsys HIGH level pulse width rise time fall time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz 36 24 36 88 59 44 781 520 390 ns ns ns
0.30Tsys - 0.40Tsys - 0.30Tsys - 0.40Tsys - - -
1 128fs
0.70Tsys ns 0.60Tsys ns 0.70Tsys ns 0.60Tsys ns 20 20 - - - 20 20 - - 80 80 - - - - - - - - - - - - - ns ns
- - - - - - - - - - - - - - - - - - - - - - - -
Serial input/output data timing; see Fig.11 bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time ns ns ns ns ns ns ns ns ns ns ns ns 30 30 - - 20 0 - - 0 20 10
td(DATAO-BCK) data output delay time (from BCK falling edge) td(DATAO-WS) th(DATAO) ts(WS) th(WS) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)DA th(L3)DA tsu(L3)DAA th(L3)DAA thalt data output delay time (from WS edge) MSB-justified format data output hold time word select set-up time word select hold time
Address and data transfer mode timing; see Fig 6 L3CLOCK cycle time L3CLOCK HIGH period L3CLOCK LOW period L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time L3DATA set-up time L3DATA hold time L3MODE halt time address mode address mode data transfer mode data transfer mode data transfer mode and address mode data transfer mode and address mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Notes: 1. Sampling range from 16 to 100 kHz is supported, with fs = 44.1 kHz typical. 2. Sampling range from 16 to 55 kHz is supported, with fs = 44.1 kHz typical.
UDA1343TT
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.10 System clock timing.
handbook, full pagewidth
WS tBCKH tr BCK tf th(WS) ts(WS)
td(DATAO-BCK)
tBCKL Tcy DATAO td(DATAO-WS)
th(DATAO)
ts(DATAI) th(DATAI) DATAI
MGL885
Fig.11 Serial interface timing.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
APPLICATION INFORMATION
UDA1343TT
The application information as given in Fig.12, is an optimum application environment. Simplification is possible at the cost of some performance degradation. The following notes apply: * The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter also changes. * The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the capacitor with the 12 k input resistance of the ADC will also change.
handbook, full pagewidth
L1 3V 8LM32A07 L2 8LM32A07 ground C12 100 F (16 V) VDDD C11 100 F (16 V) C2 100 F (16 V) C21 100 nF (63 V) VDDA
VDDA R21 1
VDDD R28 1
R24
C25 100 nF (63 V) VADCN 7 VADCP VSSD 11 VDDD 10
VSSA(ADC) VDDA(ADC) system clock R30 47 DATAO BCK WS DATAI overload flag X4 C1 47 F (16 V) X5 C6 47 F (16 V) VDDD 100 nF L3MODE L3CLOCK L3DATA 13 14 15 27 VSSO C26 100 nF (63 V) C7 100 F (16 V) 25 VINR 5 OVERFL SYSCLK 1 12 2 6
18 16 17 19 9
4
Vref(A) C22 100 nF (63 V) C3 47 F (16 V)
26 left input VINL 3
VOUTL
C5 47 F (16 V) R22 10 k
R23 100
X2
left output
UDA1343TT
right input
24
VOUTR
C8 R27 10 k
R26 100
X3
47 F (16 V) RESET 20
right output
28
Vref(D) C23 100 nF (63 V) C4 47 F (16 V)
MGL891
22 VSSA(DAC) C27 100 nF (63 V) C10 100 F (16 V)
23 VDDA(DAC)
VDDO
R25 1 VDDO
R29 1 VDDA
Fig.12 Application diagram.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
PACKAGE OUTLINE TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
UDA1343TT
SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
UDA1343TT
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1343TT
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
NOTES
UDA1343TT
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
NOTES
UDA1343TT
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Philips Semiconductors
Preliminary specification
Economy audio CODEC with features
NOTES
UDA1343TT
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/01/pp36
Date of release: 2000
Jan 12
Document order number:
9397 750 06447

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